The Senior Layout Design Engineer role offers the opportunity to work on technically challenging analogue, mixed-signal and high-performance IC layout projects within a global engineering environment. This position plays an important part in delivering silicon-proven semiconductor designs, supporting tapeout readiness and contributing to the development of advanced technology solutions through close collaboration with circuit design teams.
Responsibilities
Own and execute the full layout lifecycle for analogue and mixed-signal IP blocks, including ADCs, DACs, PLLs, LDOs, bandgaps, amplifiers and pixels.
Collaborate closely with circuit design engineers to understand design specifications, constraints and performance requirements.
Develop floorplans, layout strategies and routing plans to optimise matching, noise performance and EM/IR robustness.
Perform custom layout of critical analogue circuits using industry-standard EDA tools such as Cadence Virtuoso.
Ensure compliance with DRC, ERC, LVS and PEX requirements.
Apply advanced layout techniques including guard rings, shielding, device isolation, symmetry control and dummy placement.
Work with foundry PDKs to interpret process rules, device models and reliability requirements including ESD, EM and latch-up.
Prepare designs for tapeout, including final verification checks, documentation and coordination with fabrication teams.
Create and maintain layout documentation, checklists and internal design guidelines.
Develop scripts to automate repetitive layout tasks and improve design efficiency.
Participate in technical reviews with internal design teams and customers.
Work independently while collaborating closely with local technical leadership.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related technical field.
4 to 7+ years of experience in analogue or mixed-signal IC layout design.
Strong proficiency with Cadence Virtuoso or equivalent IC layout platforms.
Deep understanding of analogue layout matching and common centroid techniques.
Strong knowledge of low-noise and low-offset layout methodologies.
Experience with parasitic-aware layout design and optimisation.
Solid understanding of physical verification flows including DRC, LVS, PEX and related tools such as Calibre, Assura or PVS.
Ability to work effectively with circuit designers, CAD engineers, verification teams and technical leads.
Excellent communication, documentation and problem-solving skills.
Fluent English communication skills.
Benefits
Opportunity to work within a global technology organisation.
Long-term career development opportunities within a stable global company.
About the Company
A company in the electronic instruments, precision technologies and industrial solutions industry. This global organisation operates internationally and provides high-value products and solutions supporting applications across analytical instrumentation, testing and inspection, aerospace, energy, medical and industrial sectors. The company is recognised for its strong technology capabilities, global engineering expertise and long-term business growth strategy.