Clock and Reset system design leader for automotive SoC design

Publication date 2025/11/28

Work Location , Expected Annual Income :

Tokyo,6.8M ～ 11.0M

About the Company :

Support at major Japanese semiconductor manufacturing company

Responsibilities :

?Translate system requirements into concrete concepts and design targets.
?Lead the grand design of functional and verification strategies for clock, reset, and power control systems.
?Develop strategies for Design for Test (DFT) and overall testing.
?Plan and execute evaluation strategies for system characteristics.
?Provide technical leadership to logic design and verification teams.
?Collaborate with overseas design centers (India, Vietnam) using English as the working language.
?Focus on IP development for clock control, reset mechanisms, power ?control systems, and related peripheral circuits.

Benefits :

?Annual salary: 6,800,000 ? 11,000,000 (monthly base: 560,000 ? 910,000).
?Annual bonus.
?Full social insurance coverage.
?Commuting expenses fully covered.
?Housing allowance (conditions apply).
?Retirement and pension systems.
?Childcare and nursing care leave.
?Remote work, flextime, and short-time work systems available.
?Health promotion programs and regular medical checkups.
?Life and accident insurance.
?Special support programs (e.g., condolence payments, educational support for bereaved children).
?Training programs by job level and function, business skills education, and self-development support.

Required Experience / Abilities / Skills :

?Minimum 3 years of experience in clock, reset, and power control system development in digital front-end design.
?Experience in digital circuit design and verification.
?English communication skills (daily conversation level, TOEIC ~600).
?Ability to lead teams, manage progress, and work independently.
Strong interpersonal and management skills.

Contact Information :

no-doi@jac-international.jp
m-huang@jac-international.jp

JOB ID : IJB2009264