High-speed I/F design leader for automotive SoC design

Publication date 2026/02/6

Work Location , Expected Annual Income :

Tokyo,6.8M ～ 11.0M

About the Company :

global leader at semiconuctor manufacturing company

Responsibilities :

?Lead the specification and digital circuit design of high-speed interface IP for automotive SoCs.
?Translate requirements into concrete concepts and targets.
?Design functional and verification strategies.
?Develop DFT (Design for Test) and testing strategies.
?Plan performance evaluation and strategy.
?Provide technical leadership to logic design and verification teams.
?Target IP includes PCIe, UCIe, UFS, USB, MIPI-CSI2, MIPI-DSI, DisplayPort, Ethernet, DDR, and others.
?Collaborate with global design centers in India and Vietnam using English as the working language.

Benefits :

?Annual salary ranging from 6,800,000 to 11,000,000
?Annual bonus paid once per year.
?Full commuting expense reimbursement.
?Housing allowance (subject to conditions).
?Retirement and pension plans.
?Rent subsidy and employee stock ownership plan.
?Childcare and caregiving leave systems.
?Remote work and flexible working hours available.
?Health promotion programs and regular medical checkups.
?Insurance coverage including life and accident insurance.
?Special support programs (e.g., condolence payments, caregiving assistance).

Required Experience / Abilities / Skills :

?Experience in high-speed interface development for digital front-end design.
?Knowledge of one or more protocols: UCIe, PCIe6/4, Ethernet, USB, MIPI, DisplayPort.
?Understanding of physical implementation and electrical characteristics.
?English proficiency for smooth communication in a global team.
Preferred:
?Experience in package or PCB design.
?PI/SI testing experience.
?Development experience in Linux environments.
?Strong leadership, autonomy, and project management skills.

Contact Information :

m-huang@jac-international.jp

JOB ID : IJB2009270